Rapidus Eyes Eight-Reticle AI Packaging by 2030
Rapidus’s plan to manufacture eight-reticle interposers on 600 mm glass panels is a high-risk attempt to make the largest AI-class chiplet packages more economical by 2030.
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packaging covers its essential concepts, wider context, practical applications and developments across technology, business and society.
Rapidus’s plan to manufacture eight-reticle interposers on 600 mm glass panels is a high-risk attempt to make the largest AI-class chiplet packages more economical by 2030.
A reported rise in high-bandwidth-memory shipments to Malaysia is consistent with Intel preparing to expand advanced packaging in Penang, but the available trade signals do not establish that Project Pelican is the destination.
TSMC’s reported yield above 98% for its 5.5-reticle CoWoS-L packaging signals that exceptionally large AI packages are becoming manufacturable at scale, although the company’s longer-term roadmap still carries substantial execution risk.
SK hynix is pursuing a 3D DRAM-on-logic architecture for future on-device AI, but this should not be confused with TSMC’s separately reported WMCM packaging approach.
TSMC’s public roadmap shows a broad push to scale advanced packaging, but it has not formally announced a direct replica of Intel’s embedded-bridge technology.